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IP5311CX5 dual-channel integr ated passive filter network with esd protection to iec 61000-4-2 level 4 rev. 01 ? 30 november 2009 product data sheet 1. product profile 1.1 general description IP5311CX5 is a dual-channel rc low-pass filter array which is designed to provide filtering of undesired rf signals in the 10 mhz to 6 000 mhz frequency band. in addition, IP5311CX5 incorporates diodes to provide protection to downstream components from electrostatic discharge (esd) voltages as high as 15 kv contact according the iec 61000-4-2 model, far exceeding standard level 4. the device is optimized for loudspeake r applications using speakers of 10 to 32+ impedance. IP5311CX5 is fabricated using monolithic s ilicon technology and integrates several resistors, bidirectional diodes and two high density capacitors in a single wafer-level chip-scale package (wlcsp). these features make the IP5311CX5 ideal for use in applications requiring the utmost in miniat urization such as mobile phone handsets, cordless telephones and personal digital devices. 1.2 features ? pb-free, rohs compliant and free of ha logen and antimony (dark green compliant) ? dual-channel integrated rc filter netwo rk with high density capacitors (2 5 nf) ? integrated esd protection withstanding 15 kv contact discharge, far exceeding iec 61000-4-2 level 4 ? wlcsp with 0.4 mm pitch 1.3 applications ? cellular and personal communication system (pcs) mobile handsets ? cordless telephones ? wireless data (wan/lan) systems
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 2 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 2. pinning information 2.1 pinning 008aaa200 transparent top view bump a1 index area a b c 2 1 IP5311CX5/lf fig 1. pin configuration IP5311CX5/lf 2.2 pin description table 1. pinning pin description a1 filter channel 1 internal 2 kv amplifier connection a2 filter channel 1 external 15 kv speaker connection c1 filter channel 2 internal 2 kv amplifier connection c2 filter channel 2 external 15 kv speaker connection b1 not connected (missing ball) b2 ground 3. ordering information table 2. ordering information type number package name description version IP5311CX5/lf wlcsp5 wafer level chip-size package; 5 bumps; 1.16 0.8 0.61 mm IP5311CX5/lf IP5311CX5/lf/p wlcsp5 wafer level chip-size package; 5 bumps; 1.16 0.8 0.61 mm IP5311CX5/lf/p
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 3 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 4. functional diagram 008aaa20 1 a1 b2 a2 15 c1 c2 15 5 nf 5 nf fig 2. schematic diagram IP5311CX5 5. limiting values table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v i input voltage ? 0.5 +4.5 v v esd electrostatic discharge voltage pins a2 and c2 to ground contact discharge [1] ? 15 +15 kv air discharge [1] ? 15 +15 kv iec 61000-4-2 level 4; pins a2 and c2 to ground contact discharge ? 8 +8 kv air discharge ? 15 +15 kv iec 61000-4-2 level 1; pins a1 and c1 to ground contact discharge ? 2 +2 kv air discharge ? 2 +2 kv i ch channel current (dc) - 92 ma p ch channel power dissipation continuous power - 100 mw p tot total power dissipation continuous power - 200 mw t stg storage temperature ? 55 +150 c t reflow(peak) peak reflow temperature 10 s maximum - 260 c t amb ambient temperature ? 35 +85 c [1] device is qualified with 1000 pulses of 15 kv contact discharges each, according to the iec61000-4-2 model and far exceeds the specified level 4 (8 kv contact discharge).
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 4 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 6. characteristics table 4. channel characteristics t amb = 25 c; unless otherwise specified. symbol parameter conditions min typ max unit r s(ch) channel series resistance 13.5 15 16.5 c 1 capacitance 1 high density; v bias(dc) = 0 v; f = 100 khz 4 5 6 nf c 2 capacitance 2 4 5 6 nf c d diode capacitance v bias(dc) = 0 v; f = 100 khz [1] - 14 - pf v br breakdown voltage positive direction; i test = 1 ma 14 16.5 - v negative direction; i test = ? 1 ma - ? 16.5 ? 14 v i lr reverse leakage current per channel; v i = 3.0 v - - 60 na per channel; v i = ? 3.0 v ? 60 - - na [1] guaranteed by design.
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 5 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 7. application information 7.1 insertion loss the insertion loss measurement configuration of a typical 50 network analyzer (nwa) system for evaluation of the IP5311CX5 is shown in figure 3 . the insertion loss of both channels at frequencies up to 6 ghz is displayed in figure 4 . out 001aai75 5 50 50 v gen dut in test board fig 3. frequency response measurement configuration 001aak630 ? 30 ? 20 ? 40 ? 10 0 s 21 (db) ? 50 f (mhz) 10 ? 1 10 4 10 3 110 2 10 (1) (2) (1) channel 1 (pins a1 and a2). (2) channel 2 (pins c1 and c2). fig 4. measured insertion loss magnitudes
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 6 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 7.2 crosstalk the crosstalk measurement configuration of a typical 50 nwa system for evaluation of the IP5311CX5 is shown in figure 5 . the measured crosstalk within the IP5311CX5 in a 50 nwa system from one channel to the other channel is shown in figure 6 . in all cases, unused connections are terminated with 50 to ground. out_2 001aai75 6 50 50 v gen dut in_1 out_1 in_2 test board 50 50 fig 5. crosstalk measurement configuration 001aak631 ? 60 ? 40 ? 80 ? 20 0 ct (db) ? 100 f (mhz) 10 ? 1 10 4 10 3 110 2 10 (2) (1) (1) channel 1 to channel 2 (pins a1 and c2). (2) channel 2 to channel 1 (pins a2 and c1). fig 6. measured crosstalk between adjacent channels
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 7 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 7.3 voltage dependency of high density capacitors the high density capacitors integrated in IP5311CX5 show a voltage dependency similar to some higher value discrete ceramic capacitors. when used in an average mobile application, the typical voltage swing across the capacitance will be in the range of ? 0.5 v to +4 v. in this event, the capacitor values change proportional to the bias voltage as depicted in figure 7 . the measurement is performed several times, starting at the ?starting point? at 0 v, increasing to 4 v (arrow 1), decreasing to ? 0.5 v (following arrow 2) and back to +4 v (arrow 3). when measuring the capacitance over voltage for voltage swings of e.g. ? 20 v to +20 v, a hysteresis in the capacitance over v bias(dc) can be observed (see figure 8 ), which is inherent to the integration process for the high density capacitors in this product. again, the measurement starts at ?starting point?, following arrow 1 up to v bias(dc) = 20 v, from there along arrow 2 down to v bias(dc) = ? 20 v and back via arrow 3 and arrow 4. values of c 1 and c 2 specified in ta b l e 4 are based on measurements at the starting point. v bias(dc) (v) ? 0.5 4.5 3.5 1.5 2.5 0.5 001aak632 0.95 0.85 1.05 1.15 c/c (0v) 0.75 starting point 2 1 3 v bias(dc) (v) ? 20 20 10 ? 10 0 001aak633 0.5 0.75 0.25 1 1.25 c/c (0v) 0 starting point 2 1 4 3 fig 7. relative capacitance c/c (0v) of high density capacitors for ? 0.5 v v bias(dc) +4 v fig 8. relative capacitance c/c (0v) of high density capacitors for ? 20 v v bias(dc) +20 v
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 8 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 8. package outline references outline version european projection issue date iec jedec jeita IP5311CX5/lf IP5311CX5_lf_po unit mm max nom min 0.66 0.61 0.56 0.22 0.20 0.18 0.31 0.26 0.21 0.85 0.80 0.75 1.21 1.16 1.11 0.40 a dimensions w lcsp5: wafer level chip-size package; 5 bumps; 1.16 x 0.8 x 0.61 mm IP5311CX5/l f a 1 a 2 0.44 0.41 0.38 bdee 0 1 scale 2 mm 2 1 c b a e b x detail x a a 2 a 1 d e laser marking area bump a1 index area 09-09-03 09-10-30 fig 9. package outline IP5311CX5/lf (wlcsp5)
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 9 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 9. soldering of wlcsp packages 9.1 introduction to soldering wlcsp packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering wlcsp (wafer level chip-size packages) can be found in application note an10439 ?wafer level chip scale package? and in application note an10365 ?surface mount reflow soldering description? . wave soldering is not su itable for this package. all nxp wlcsp packages are lead-free. 9.2 board mounting board mounting of a wlcsp requires several steps: 1. solder paste printing on the pcb 2. component placement with a pick and place machine 3. the reflow soldering itself 9.3 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 10 ) than a pbsn process, thus reducing the process window ? solder paste printing issues, such as sm earing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature), and coo ling down. it is imper ative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 5 . table 5. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2 000 > 2 000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 10 .
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 10 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature msl: moisture sensitivity level fig 10. temperature profiles for large and small components for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 9.3.1 stand off the stand off between the substrate and the chip is determined by: ? the amount of printed solder on the substrate ? the size of the solder land on the substrate ? the bump height on the chip the higher the stand off, the better the stresses are released due to tec (thermal expansion coefficient) differences between substrate and chip. 9.3.2 quality of solder joint a flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. the surface of the joint should be smooth and the shape symmetrical. the soldered joints on a chip should be uniform. voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. no failures have been found to be related to these voids. solder joint inspection after reflow can be done with x-ray to monitor defects such as bridging, open circuits and voids. 9.3.3 rework in general, rework is not recommended. by rework we mean the process of removing the chip from the substrate and replacing it with a new chip. if a chip is removed from the substrate, most solder balls of the chip will be damaged. in that case it is recommended not to re-use the chip again.
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 11 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network device removal can be done when the substrate is heated until it is certain that all solder joints are molten. the chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. removing the device must be done using plastic tweezers, because me tal tweezers can damage the silicon. the surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill remove d. when a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. apply flux on the bumps at the chip side as well as on the solder pads on the substrate. place and align the new chip while viewing with a microscope. to reflow the solder, use the solder profile shown in application note an10365 ?surface mount reflow soldering description? . 9.3.4 cleaning cleaning can be done after reflow soldering. 10. abbreviations table 6. abbreviations acronym description dut device under test esd electrostatic discharge lan local area network nwa network analyzer pcs personal communication system rohs restriction of hazardous substances wan wide area network wlcsp wafer-level chip-scale package 11. revision history table 7. revision history document id release date data sheet status change notice supersedes IP5311CX5_1 20091130 product data sheet - -
IP5311CX5_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 ? 30 november 2009 12 of 13 nxp semiconductors IP5311CX5 dual-channel integrated passive filter network 12. legal information 12.1 data sheet status document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objec tive specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 12.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 12.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors d oes not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and condit ions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writ ing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 12.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 13. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors IP5311CX5 dual-channel integrated passive filter network ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 30 november 2009 document identifier: IP5311CX5_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 14. contents 1 product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 general description . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 pinning information . . . . . . . . . . . . . . . . . . . . . . 2 2.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 application information. . . . . . . . . . . . . . . . . . . 5 7.1 insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.3 voltage dependency of high density capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 soldering of wlcsp packages. . . . . . . . . . . . . 9 9.1 introduction to soldering wlcsp packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9.2 board mounting . . . . . . . . . . . . . . . . . . . . . . . . 9 9.3 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . 9 9.3.1 stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9.3.2 quality of solder joint . . . . . . . . . . . . . . . . . . . 10 9.3.3 rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9.3.4 cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 12 legal information. . . . . . . . . . . . . . . . . . . . . . . 12 12.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 12.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 contact information. . . . . . . . . . . . . . . . . . . . . 12 14 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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